/*
 * @Author       : Xu Xiaokang
 * @Email        : xuxiaokang_up@qq.com
 * @Date         : 2022-10-31 16:53:45
 * @LastEditors  : Xu Xiaokang
 * @LastEditTime : 2022-11-09 11:13:46
 * @Filename     :
 * @Description  :
*/

/*
! 模块功能: uart收发，实现环路测试，即将接收到的数据发出来
* 思路:
  1.
*/

module uartLoopTop
(
  input  logic uart_rx,
  output logic uart_tx,

  input logic fpga_input_clk_p,
  input logic fpga_input_clk_n,
  input logic rstn
);


//++ 时钟与复位 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
logic clk;
clk_wiz_0  clk_wiz_0_u0 (
  .clk_in1_p (fpga_input_clk_p),
  .clk_in1_n (fpga_input_clk_n),
  .clk_out1  (clk        )
);
//-- 时钟与复位 ------------------------------------------------------------


// ++ 参数设置 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
localparam CLK_FREQ_MHZ = 100;
localparam BAUD         = 115200; // 波特率, 9600, 19200, 38400, 57600, 115200, 230400, 460800, 921600
localparam DATA_BITS    = 8;      // 数据位宽度, 可选5, 6, 7, 8
localparam PARITY       = "ODD";  // 校验 "NONE", "ODD", "EVEN", "MARK", "SPACE"
localparam STOP_BITS    = 2;    // 停止位宽度, 可选1, 1.5, 2
// -- 参数设置 ------------------------------------------------------------


//++ 实例化uart模块 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
(* mark_debug *) logic rx_cclk_fwft_fifo_8wxxd_full;
(* mark_debug *) logic [7 : 0] rx_cclk_fwft_fifo_8wxxd_din;
(* mark_debug *) logic rx_cclk_fwft_fifo_8wxxd_wr_en;
(* mark_debug *) logic rdata_error;

(* mark_debug *) logic tx_cclk_fwft_fifo_8wxxd_empty;
(* mark_debug *) logic [7 : 0] tx_cclk_fwft_fifo_8wxxd_dout;
(* mark_debug *) logic tx_cclk_fwft_fifo_8wxxd_rd_en;

uartRTUseFIFO #(
  .CLK_FREQ_MHZ (CLK_FREQ_MHZ),
  .BAUD         (BAUD),
  .DATA_BITS    (DATA_BITS),
  .PARITY       (PARITY),
  .STOP_BITS    (STOP_BITS)
) uartRTUseFIFO_u0 (
  .rx_cclk_fwft_fifo_8wxxd_full  (rx_cclk_fwft_fifo_8wxxd_full ),
  .rx_cclk_fwft_fifo_8wxxd_din   (rx_cclk_fwft_fifo_8wxxd_din  ),
  .rx_cclk_fwft_fifo_8wxxd_wr_en (rx_cclk_fwft_fifo_8wxxd_wr_en),
  .rdata_error                   (rdata_error                  ),
  .tx_cclk_fwft_fifo_8wxxd_empty (tx_cclk_fwft_fifo_8wxxd_empty),
  .tx_cclk_fwft_fifo_8wxxd_dout  (tx_cclk_fwft_fifo_8wxxd_dout ),
  .tx_cclk_fwft_fifo_8wxxd_rd_en (tx_cclk_fwft_fifo_8wxxd_rd_en),
  .uart_tx                       (uart_tx                      ),
  .uart_rx                       (uart_rx                      ),
  .clk                           (clk                          ),
  .rstn                          (rstn                         )
);
//-- 实例化uart模块 ------------------------------------------------------------


//++ 实例化FWFT FIFO ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
cclk_fwft_fifo_8w1024d cclk_fwft_fifo_8w1024d_u0 (
  .clk   (clk  ), // input wire clk
  .srst  (~rstn ), // input wire srst

  .din   (rx_cclk_fwft_fifo_8wxxd_din  ), // input wire [7  : 0] din
  .wr_en (rx_cclk_fwft_fifo_8wxxd_wr_en), // input wire wr_en
  .full  (rx_cclk_fwft_fifo_8wxxd_full ), // output wire full

  .rd_en (tx_cclk_fwft_fifo_8wxxd_rd_en), // input wire rd_en
  .dout  (tx_cclk_fwft_fifo_8wxxd_dout ), // output wire [7 : 0] dout
  .empty (tx_cclk_fwft_fifo_8wxxd_empty)  // output wire empty
);
//-- 实例化FWFT FIFO ------------------------------------------------------------


endmodule